My area of emphasis is chip-to-chip communications, including high-speed circuit design, data encoding and signal / power integrity. I presently lead Micron's Interface Pathfinding Group which focuses on exploring / developing new signaling solutions to continue to scale speed / power performance beyond the 5-10 year horizon. I am a Micron Fellow and a Senior Member of the IEEE. I have led local IEEE workshops and served on the program committees for a variety of conferences. I served as the Technical Editor of the IEEE Solid State Circuits magazine and guest edited two issues of the magazine. As a college student I interned twice with Micron and once with Intel. I have experience working at Micron, Intel, and Qualcomm, so I have seen a variety of working environments. I started my engineering career a little later in life, having graduated with a BS in Psychology from BYU before starting in engineering.