Students

Current Students

Name	Program	Project Title
Travis Haroldsen	PhD	Physical Design CAD Tools for FPGAs
Jon-Paul Anderson	PhD	Smart-Model Based Detection for Reduced Cost FPGA Reliability in Harsh Environments
Thomas Townsend	MS	Graphical Design Environments for FPGA-Based Systems

Former Students

Name	Degree	Year	Thesis Title
Brad White	MS	2014	Tincr: Integrating Custom CAD Tool Frameworks with the Xilinx Vivado Design Suite
Christopher Lavin	PhD	2012	Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs
Yubo (Robert) Li	PhD	2012	Reliability Techniques for Data Communication and Storage in FPGA-Based Circuits
Marc Padilla	MS	2011	FM Demodulators in Software-Defined Radio Using FPGAs With Rapid Prototyping
Kevin Ellsworth	MS	2012	Understanding Design Requiremewnts for Building Reliable, Space-Based FPGA MGT Systems Based on Radiation Test Results
Subhra Gosh	MS	2011	XDL Based Hard Macro Generator
Joseph Palmer	PhD	2009	Real-Time Carrier Frequency Estimation Using Disjoint Pilot Symbol Blocks
John M. Bodily	MS	2009	An Optical Flow Implementation Comparison Study
Joseph Palmer	MS	2005	The Hybrid Architcture Parallel Fast Fourier Transform (HAPFFT)
Bryan C. Catanzaro	MS	2005	Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Clint Hilton	MS	2005	A Flexible Circuit-Switched Communication Network for FPGA-Based SOC Design
Gregory Ahlquist	PhD	2004	Functionally Decomposing Finite Field Multiplierts for Efficient Implementation on Field Programmable Gate Arrays
Xiaojun Wang	MS	2003	Tradeoffs of Designing Floating-Point Division and Square Root On Virtex FPGAs
Eric Roesler	MS	2003	A Simulation and Hardware Execution Co-Verification Environment For Soft-Core CPUs
Anthony Slade	MS	2003	Designing, Debugging, and Deploying Configurable Computing Machine-Based Applications Using Reconfigurable Computing Application Frameworks
Paul Graham	PhD	2001	Logical Hardware Debuggers For FPGA-Based Systems
Timothy Wheeler	MS	2001	Improving Design Observability and Controllability For Functional Verification of FPGA-Based Circuits Using Design-Level Scan Techniques
Russell Frederickson	MS	2001	Constant Coefficient Multiplication
Jeremy Anderson	MS	2000	Module Generation for FPGAs
Matthew. Severson	MS	2000	Relational Placement and Layout Manipulation With JHDL for FPGAs
Michael Rytting	MS	2000	Using JHDL To Visualize, Debug, and Execute External Designs
Paul Graham	MS	1996	A Description, Analysis, and Comparison of a Hardware and a Software Implementation of the Splash Genetic Algorithm for Optimizing Symmetric Traveling Salesman Problems
Gregory Thompson	MS	1995	Memory Hierarchy Performance of Transaction Processing Workloads
Cameron McNairy	MS	1995	A Linear System of Equations Solver on Splash-2 -- A Systolic Approach
J. Kelly Flanagan	PhD	1993	A New Methodology for Accurate Trace Collection and Its Application to Memory Hierarchy Performance Modeling
Paul Michelsen	MS	1992	Optimization of the Numerically Intensive ACERC Combustion Code For Execution on the New Super-Workstations
Curtis Collyer	MS	1992	A Timing Analysis of Two-Level Cache Memory Systems
J. Kelly Flanagan	MS	1989	Processor Design Using Path Programmable Logic
Robert Martell	MS	1988	Systolic Array Simulator: SYSTOLE
Roger Pennington	MS	1988	FPM: A Low Cost Floating Point Audio Signal Processor
Gary Brown	MS	1986	A Port Reordering Algorithm to Reduce Interconnect Length and Crossovers for Improved Routability of Integrated Circuits
Darryl Morrell	MS	1986	Compaction of Constrained Tiled Circuits Using Monte Carlo Algorithms
Brian Moore	MS	1986	A Pipelined Floating-Point Systolic Array Arithmetic Processor

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